Upstream: the sun9i display series #50

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opened 2026-08-28 14:22:12 +00:00 by tiagoagueda · 0 comments

tiagoagueda commented

2026-08-28 14:22:12 +00:00

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Four fixes now produce a picture on sun9i, exported to
patches/linux-drm-sun9i-display/:

sun6i_drc: program the DRC (size, identity CSC, double-buffer latch) and take the
ram clock the binding has always described
backend: the layer address fixup and the global-alpha fix for formats with no alpha
channel
tcon: needs_de_be_mux for the A80

Not ready to send, for concrete reasons:

the address fixup in (2) is empirical - see the separate issue on the DMA/physical
mismatch. It must not go anywhere until the root cause is known.
the DRC gets its size handed down the of_graph link from the backend's mode_set. That
plumbing is provisional and wants a better shape; the DRC is not a DRM component with a
mode of its own and probably should be.
the global-alpha change touches every sunxi SoC and needs testing on at least one other,
which this project cannot do.

The ram clock fix and the TCON mux quirk are the two that are close to sendable on their
own merit.

⚠️ Read 42-upstreaming.md first. Nothing here has
been sent anywhere.

Done when

the series is split into what is genuinely defensible and that part is proposed

Four fixes now produce a picture on sun9i, exported to [patches/linux-drm-sun9i-display/](../src/branch/main/patches/linux-drm-sun9i-display/): 1. `sun6i_drc`: program the DRC (size, identity CSC, double-buffer latch) and take the `ram` clock the binding has always described 2. `backend`: the layer address fixup and the global-alpha fix for formats with no alpha channel 3. `tcon`: `needs_de_be_mux` for the A80 **Not ready to send**, for concrete reasons: - the address fixup in (2) is empirical - see the separate issue on the DMA/physical mismatch. It must not go anywhere until the root cause is known. - the DRC gets its size handed down the of_graph link from the backend's `mode_set`. That plumbing is provisional and wants a better shape; the DRC is not a DRM component with a mode of its own and probably should be. - the global-alpha change touches every sunxi SoC and needs testing on at least one other, which this project cannot do. The `ram` clock fix and the TCON mux quirk are the two that are close to sendable on their own merit. ⚠️ Read [42-upstreaming.md](../src/branch/main/42-upstreaming.md) first. Nothing here has been sent anywhere. **Done when** - [ ] the series is split into what is genuinely defensible and that part is proposed

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2026-08-28 14:22:12 +00:00