U-Boot: splash logo on HDMI (needs a sun9i display driver) #51

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opened 2026-08-28 14:32:21 +00:00 by tiagoagueda · 0 comments

tiagoagueda commented

2026-08-28 14:32:21 +00:00

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Nice to have, not needed for anything. Filed so the register knowledge is captured
while it is fresh.

A picture works under Linux (#22). Showing one from U-Boot is a different job, because
U-Boot has no display support for the A80 at all:

driver	covers
`drivers/video/sunxi/sunxi_display.c`	DE1 on A10-A33 (sun4i..sun8i)
`drivers/video/sunxi/sunxi_de2.c`	DE2 on A64/H3/H5/R40
`drivers/video/sunxi/sunxi_dw_hdmi.c`	DesignWare HDMI glue, used with DE2

grep -rl sun9i drivers/video/ returns nothing, and our .config has zero VIDEO,
SPLASH or BMP options enabled.

The A80 falls between the two families: it is DE1, but with the mandatory DRC and CMU
stages that sunxi_display.c knows nothing about - the blocks that took a whole session to
work out in #22.

What it would take

Essentially reimplementing the kernel work in U-Boot:

backend layer setup, including both quirks: the bit-encoded address with its
0x20000000 offset, and the global alpha for formats with no alpha channel
the DRC: size, identity CSC over the BT.709 matrix it holds at reset, the double-buffer
latch, enable
TCON1 timings, plus TCON1_Src_Sel = 01 (DE 1)
DesignWare HDMI bring-up: PHY, EDID, mode set

Two things make this tractable rather than speculative:

sunxi_dw_hdmi.c already exists and is the same IP family (DW HDMI TX)
every register value that works is now known and verified on this hardware - see
46-hdmi-picture.md and
patches/linux-drm-sun9i-display/

sunxi_display.c is a reasonable structural template for a DE1 pipeline.

Also

U-Boot's splash wants a BMP, not a JPEG - CONFIG_SPLASH_SCREEN plus
CONFIG_CMD_BMP, with the image in a partition or embedded in the image. Converting the
file is trivial; the driver is the work.

Rough shape: a day or two of genuinely new code.

Done when

U-Boot can put an image on HDMI on this board, or it is decided not to bother

**Nice to have, not needed for anything.** Filed so the register knowledge is captured while it is fresh. A picture works under Linux (#22). Showing one from U-Boot is a different job, because **U-Boot has no display support for the A80 at all**: | driver | covers | |---|---| | `drivers/video/sunxi/sunxi_display.c` | DE1 on A10-A33 (sun4i..sun8i) | | `drivers/video/sunxi/sunxi_de2.c` | DE2 on A64/H3/H5/R40 | | `drivers/video/sunxi/sunxi_dw_hdmi.c` | DesignWare HDMI glue, used with DE2 | `grep -rl sun9i drivers/video/` returns nothing, and our `.config` has zero `VIDEO`, `SPLASH` or `BMP` options enabled. The A80 falls between the two families: it is DE1, but with the mandatory DRC and CMU stages that `sunxi_display.c` knows nothing about - the blocks that took a whole session to work out in #22. ## What it would take Essentially reimplementing the kernel work in U-Boot: - backend layer setup, **including both quirks**: the bit-encoded address with its `0x20000000` offset, and the global alpha for formats with no alpha channel - the DRC: size, identity CSC over the BT.709 matrix it holds at reset, the double-buffer latch, enable - TCON1 timings, plus `TCON1_Src_Sel = 01` (DE 1) - DesignWare HDMI bring-up: PHY, EDID, mode set Two things make this tractable rather than speculative: - `sunxi_dw_hdmi.c` already exists and is the same IP family (DW HDMI TX) - **every register value that works is now known and verified on this hardware** - see [46-hdmi-picture.md](../src/branch/main/46-hdmi-picture.md) and [patches/linux-drm-sun9i-display/](../src/branch/main/patches/linux-drm-sun9i-display/) `sunxi_display.c` is a reasonable structural template for a DE1 pipeline. ## Also U-Boot's splash wants a **BMP**, not a JPEG - `CONFIG_SPLASH_SCREEN` plus `CONFIG_CMD_BMP`, with the image in a partition or embedded in the image. Converting the file is trivial; the driver is the work. Rough shape: a day or two of genuinely new code. **Done when** - [ ] U-Boot can put an image on HDMI on this board, or it is decided not to bother

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2026-08-28 14:32:21 +00:00