sun9i-a80 has no GPU device tree node #57

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opened 2026-08-29 15:40:47 +00:00 by tiagoagueda · 0 comments

tiagoagueda commented

2026-08-29 15:40:47 +00:00

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Part of #55. Mainline has the GPU clocks but no node describing the block.

ccu-sun9i-a80.c already defines pll_gpu, gpu_core, gpu_memory, gpu_axi and the
bus-gpu-ctrl gate, so no clock work is needed. What is missing is the node itself, and any
sun9i power-domain driver (drivers/soc/sunxi/ has only arisc, mbus, sram).

Draft

gpu: gpu@2000000 {
    compatible = "allwinner,sun9i-a80-gpu";
    reg = <0x02000000 0x01000000>,   /* RGX registers */
          <0x01c08000 0x1000>;       /* GPU_CTRL      */
    reg-names = "rogue", "gpu-ctrl";
    interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&ccu CLK_PLL_GPU>, <&ccu CLK_GPU_CORE>,
             <&ccu CLK_GPU_MEMORY>, <&ccu CLK_GPU_AXI>,
             <&ccu CLK_BUS_GPU_CTRL>;
    clock-names = "pll", "core", "mem", "axi", "bus";
    resets = <&ccu RST_BUS_GPU_CTRL>;
    gpu-supply = <&dcdc3_reg>;
    status = "disabled";
};

Open points

Confirm a GPU reset index actually exists in the CCU; the vendor sequence does not obviously
assert one, so this may be the bus-gpu-ctrl gate only.
Identify which regulator axp15_dcdc3 is in our AXP806 DT before powering anything.
Same class of mistake as the aldo3 rail in #16 / #21 - do not skip.
Power domain: the vendor uses no PD framework, only writel(1 << 8, GPU_CTRL + 0x18) plus
clock gating. Reproduce exactly that first; write a pmdomain/sunxi driver only if the GPU
will not leave reset.

The vendor order is: pll_gpu -> gpu_core -> gpu_mem -> gpu_axi, then the GPU_CTRL bit,
then the bus gate. Regulator enable is separate, driven from a V/F table.

Part of #55. Mainline has the GPU clocks but no node describing the block. `ccu-sun9i-a80.c` already defines `pll_gpu`, `gpu_core`, `gpu_memory`, `gpu_axi` and the `bus-gpu-ctrl` gate, so **no clock work is needed**. What is missing is the node itself, and any sun9i power-domain driver (`drivers/soc/sunxi/` has only arisc, mbus, sram). ## Draft ```dts gpu: gpu@2000000 { compatible = "allwinner,sun9i-a80-gpu"; reg = <0x02000000 0x01000000>, /* RGX registers */ <0x01c08000 0x1000>; /* GPU_CTRL */ reg-names = "rogue", "gpu-ctrl"; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_PLL_GPU>, <&ccu CLK_GPU_CORE>, <&ccu CLK_GPU_MEMORY>, <&ccu CLK_GPU_AXI>, <&ccu CLK_BUS_GPU_CTRL>; clock-names = "pll", "core", "mem", "axi", "bus"; resets = <&ccu RST_BUS_GPU_CTRL>; gpu-supply = <&dcdc3_reg>; status = "disabled"; }; ``` ## Open points - [ ] Confirm a GPU reset index actually exists in the CCU; the vendor sequence does not obviously assert one, so this may be the `bus-gpu-ctrl` gate only. - [ ] **Identify which regulator `axp15_dcdc3` is in our AXP806 DT before powering anything.** Same class of mistake as the `aldo3` rail in #16 / #21 - do not skip. - [ ] Power domain: the vendor uses no PD framework, only `writel(1 << 8, GPU_CTRL + 0x18)` plus clock gating. Reproduce exactly that first; write a `pmdomain/sunxi` driver only if the GPU will not leave reset. The vendor order is: `pll_gpu` -> `gpu_core` -> `gpu_mem` -> `gpu_axi`, then the `GPU_CTRL` bit, then the bus gate. Regulator enable is separate, driven from a V/F table.

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2026-08-29 15:40:47 +00:00

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2026-08-29 15:41:18 +00:00

PowerVR G6230: bring the GPU up under mainline Linux #55

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2026-08-29 15:41:18 +00:00

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